MfpgaSetRegister

See also

User Guide:

Setting and retrieving results from PU registers Steps to develop a function that performs an operation using a Processing FPGA

Availability

Available in MIL-Lite

Available in MIL

Available on Windows

Available on Linux

Not supported on:

Not supported on Host system (a)

Not supported on Matrox GigE Vision driver (MIL 10, Update 25, Update 54, or Update 85)* (c)

Not supported on Matrox Morphis (g)

Not supported on Matrox Morphis QxT (h)

Not supported on Matrox Orion HD (i)

Not supported on Matrox USB3 Vision driver (Update 19) (o)

Not supported on Matrox Iris GTR (Update 28 or Update 68) (t)

Not supported on Matrox Clarity UHD (Update 36 or 76) (u)

Not supported on Matrox GenTL driver (Update 34) (v)

Not supported on Matrox Indio (Update 53 or Update 68) (w)

Not supported on Matrox Concord PoE with ToE (Update 82) (z)

Fully supported on:

Fully supported on Matrox Radient eCL (j)

Fully supported on Matrox Radient eV-CXP (MIL 10 or Update 29)* (k)

Fully supported on Matrox Solios eA/XA (l)

Fully supported on Matrox Solios ecl/xcl/ev-cl (m)

Fully supported on Matrox RadientPro-CL (Update 7) (p)

Fully supported on Matrox Radient eV-CL (Update 27 or 74) (r)

Fully supported on Matrox Rapixo CXP (Update 75 or Update 84) (y)

Fully supported on Matrox Rapixo CL Pro (Update 96) (aa)

* Refer to the MIL system-specific information
in the MIL Reference for the minimum update required.

For any information regarding a MIL system added during a MIL Update, see the MIL system’s release note

Available on Non-Matrox computer

Available on Matrox 4Sight-X

Available on Matrox 4Sight GP/GPm

Available on Matrox Supersight

Function map

Examples

fdkoffsetgainlutmapprimitive.cpp
fdkoffsetgainprimitive.cpp
lutmapprimitive.cpp

Function Map

Table:

For register space access

- Offset

- Length

- ValuePtr

- WriteAccessFlag

Table:

For specifying when to access the register

Compilation information

Synopsis

Set the contents of one or more FPGA registers.

Syntax

void MfpgaSetRegister(

MIL_FPGA_CONTEXT FpgaCommandContext,	//in
MIL_INT64 RegisterSection,	//in
MIL_INT Offset,	//in
MIL_INT Length,	//in
void *ValuePtr,	//out
MIL_INT64 WriteAccessFlag	//in

)

Description

This function writes values to FPGA registers of the PU associated with the specified command context. A maximum of four MfpgaSetRegister() calls can be made with any FPGA command context, although you can set the contents of multiple registers in each call. For a Matrox PU, you should consult the register file of the PU in the Matrox FPGA Components Reference. You can specify whether write accesses will be collected and made before processing. Note that for those PUs that have interrupts you can specify that write accesses will be collected after the PU issues its end-of-processing interrupt.

For Matrox PUs and custom PUs created using the Matrox Processing Unit Designer, a C structure is created to represent each register of the PU. The structures are supplied in header files (fpga_*.h), located in the \Matrox Imaging\MIL\Examples\SoliosFDK\Include directory for Matrox Solios and in the Matrox Imaging\radient\src\headers\local\fpga_*.h directory for Matrox Radient. You must include the appropriate header file to use the structures. See the Setting and retrieving results from PU registers section of Chapter 52: Using MIL with a Processing FPGA for more information on the Matrox register structure.

Note that this function reference has not been updated for a MIL system added during a MIL update. Refer to the MIL system's release note to see which MIL system’s documentation you should use in its place and any possible differences.

Parameters

This function is not supported on the selected boards.

This function reference has not been updated for the selected MIL system. To show the content of this page, choose a second MIL system; refer to the MIL system's release note to see which MIL system’s documentation to choose and any possible differences.

Parameters

FpgaCommandContext

Specifies the handle of the FPGA command context associated with the PU.

RegisterSection

Specifies the section of the PU's register space to access. You must set this parameter to the following value:

For register space access
Value	Description	MIL system-specific tooltip (‡)
M_USER	Specifies to access the user-specific section of the PU's register space.	‡	j	k M10	l	m	p	r U27	y U75	aa

Offset

Specifies the offset from the start of the specified register section, from which to begin writing, in bytes. The offset must be a multiple of 4 bytes.

Length

Specifies the number of bytes to write in the register. The length must be a multiple of 4 bytes.

ValuePtr

Specifies the address of the variable in which to write the value to be sent to the register.

WriteAccessFlag

Specifies when the register write access must take place. This parameter must be set to one of the following values:

For specifying when to access the register
Value	Description	MIL system-specific tooltip (‡)
M_WHEN_COMPLETED	Accesses the registers after the PU issues its end-of-processing interrupt.	‡	j	k M10	l	m	p	r U27	y U75	aa
M_WHEN_DISPATCHED	Accesses the registers during PU setup, prior to the start of processing.	‡	j	k M10	l	m	p	r U27	y U75	aa

Compilation information

Header	Include mil.h; milfpga.h.
Library	Use mil.lib; milfpga.lib.
DLL	Requires mil.dll; milfpga.dll.