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Processing an image with a Processing FPGA

To process images using a Processing FPGA, perform the following steps:

  1. Use the MILConfig utility to select the FPGA configuration with which to program the Processing FPGA. When you select a Matrox FPGA configuration, the MILConfig utility will list all the PUs that are in this particular configuration. For a description of PUs and their interconnections, refer to the Matrox FPGA Components Reference help file.

    Note that a valid Matrox FPGA configuration file has a (.mbf) or ( .firmware) extension and can be found in the Matrox Imaging\Drivers\Board_Name\Firmware\Processing folder (for example, Board_Name should be Solios in the case of a Matrox Solios board).

  2. Call the MsysAlloc() function to load the configuration in the Processing FPGA. To load a different FPGA configuration from within your application, you can use MfpgaLoad(). You must include the MIL FPGA header file milfpga.h to make a call to any Mfpga module function.

    Note that for Matrox boards with on-board processors, you can load the Matrox FPGA configuration with the MILConfig utility. Changing the selected Matrox FPGA configuration will cause the Matrox board with on-board processor to reload its FPGA.

  3. Grab the image(s) into one or more on-board FPGA-accessible buffer(s) (MbufAlloc...() with M_GRAB + M_FPGA_ACCESSIBLE).

  4. Process the images using one of the following techniques:

    • Call the required MIL function equivalent to the PU(s) in the loaded FPGA configuration.

    • Set up and call the primitive function (or the user-defined MIL function) that dispatches the required commands to the Processing FPGA on board. To set up the primitive function (or the user-defined MIL function), see the Steps to develop a function that performs an operation using a Processing FPGA section later in this chapter.

    Note that processing can typically be performed by the Processing FPGA if the source buffer is allocated on-board, the destination buffer is allocated in non-paged Host memory or on-board, and the FPGA configuration includes a path from the PU(s) to the memory banks in which the specified source and destination buffers are located. In the case of Matrox imaging boards with on-board processors, destination buffers cannot be in Host memory; only on-board destination buffers are supported. Using the M_FPGA_ACCESSIBLE attribute when allocating a buffer ensures that the buffer is in memory accessible to the Processing FPGA, although there might not be an available path between the PU and the memory bank, depending on the selected FPGA configuration.

    Note that if calling a standard MIL function that is not associated to the PU(s) in the loaded FPGA configuration, the Host will process the image(s), but the processing might be significantly slower than normal if the images are on-board.

    If calling a primitive function and the target PU is not in the loaded FPGA configuration, an error is generated.