| MIL 10 Reference
| Customize Help
| Save Settings

MfpgaGetRegister



See also
Availability
Available in MIL-Lite
Available in MIL

Available on Windows
Available on Linux

Not supported on:
Not supported on Host system
Not supported on Matrox CronosPlus
Not supported on Matrox GPU processing driver
Not supported on Matrox GigE Vision driver
Not supported on Matrox IEEE 1394 IIDC driver
Not supported on Matrox Iris GT
Not supported on Matrox Morphis
Not supported on Matrox Morphis QxT
Not supported on Matrox Orion HD
Not supported on Matrox USB3 Vision driver (requires Update 19)
Not supported on Matrox Vio
Fully supported on:
Fully supported on Matrox Radient eCL
Fully supported on Matrox Radient eV-CXP
Fully supported on Matrox Solios eA/XA
Fully supported on Matrox Solios ecl/xcl/ev-cl

For any information regarding a MIL system added during a MIL Update, see the MIL system’s release note

Available on Non-Matrox computer
Available on Matrox 4Sight-X
Available on Matrox 4Sight GP
Available on Matrox Supersight
function map Function map
Examples
Synopsis
Set up a request to read registers of a PU.
Syntax
void MfpgaGetRegister(
MIL_FPGA_CONTEXT FpgaCommandContext, //in
MIL_INT64 RegisterSection, //in
MIL_INT Offset, //in
MIL_INT Length, //in
void *ValuePtr, //out
MIL_INT64 ReadAccessFlag //in
)
Description

This function sets up a request to read registers of the PU associated with the specified command context. A maximum of four MfpgaGetRegister() calls can be made with any FPGA command context, although you can return the contents of multiple registers with each call. For a Matrox PU, you should consult the register file of the PU in the Matrox FPGA Components Reference. You can specify whether read accesses will be collected and made before processing or after the PU issues its end-of-processing interrupt.

For Matrox PUs and custom PUs created using the Matrox Processing Unit Designer, a C structure is created to represent each register of the PU. The structures are supplied in header files (fpga_*.h), located in the \Matrox Imaging\MIL\Examples\SoliosFDK\Include directory for Matrox Solios and in the Matrox Imaging\radient\src\headers\local\fpga_*.h directory for Matrox Radient. You must include the appropriate header file to use the structures. See the Setting and retrieving results from PU registers section of Chapter 34: Using MIL with a Processing FPGA for more information on the Matrox register structure.

Note that this function reference has not been updated for a MIL system added during a MIL update. Refer to the MIL system's release note to see which MIL system’s documentation you should use in its place and any possible differences.
Parameters
This function is not supported on the selected boards.
This function reference has not been updated for the selected MIL system. To show the content of this page, choose a second MIL system; refer to the MIL system's release note to see which MIL system’s documentation to choose and any possible differences.
Parameters
FpgaCommandContext

Specifies the handle of the FPGA command context associated with the PU. The command context must have been previously allocated on the system using MfpgaCommandAlloc().

RegisterSection

Specifies the section of the PU's register space to access. You must set this parameter to the following value:

function map For register space access
CollapseValue Description
MIL system-specific
tooltip (†)
Collapse M_USER

Specifies to access the user-specific section of the PU's register space.

j k l m p q r
Offset

Specifies the offset from the start of the specified register section, from which to begin reading, in bytes. The offset must be a multiple of 4 bytes.

Length

Specifies how many bytes of the register to read. The length must be a multiple of 4 bytes.

ValuePtr

Specifies the address of the variable in which to write the value read from the register. This address must remain valid for the duration of the operation, otherwise a memory corruption will occur.

ReadAccessFlag

Specifies when the register read access must take place. This parameter must be set to one of the following values:

function map For specifying when to read the register
CollapseValue Description
MIL system-specific
tooltip (†)
Collapse M_WHEN_COMPLETED

Accesses the registers after the PU finishes processing (according to MfpgaCommandQueue() completion mode).

j k l m p q r
Collapse M_WHEN_DISPATCHED

Accesses the registers during PU setup, prior to the start of processing.

j k l m p q r
Compilation information
Header Include mil.h; milfpga.h.
Library Use mil.lib; milfpga.lib.
DLL Requires mil.dll; milfpga.dll.
USER WHEN COMPLETED WHEN DISPATCHED