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Matrox Solios eA/XA connectors and signal names



This section serves as a reference to match Matrox Solios eA/XA's connectors and auxiliary signals with MIL information, such as MIL auxiliary signal numbers. To set/inquire all the settings for this board's auxiliary signals (for example, signal routing and timer settings), use MdigControl() / MdigInquire(), respectively.

Matrox Solios eA/XA has three versions, each with a different number of acquisitions paths and auxiliary signals. For each version of Matrox Solios eA/XA, only the auxiliary signals associated with he following digitizer device numbers are supported:

Matrox Solios type

Digitizer device #

Matrox Solios eA/xA (Single)

M_DEV0.

Matrox Solios eA/xA (Dual)

M_DEV0 and M_DEV1.

Matrox Solios eA/xA (Quad)

M_DEV0, M_DEV1, M_DEV2, and M_DEV3.

The following table lists the connectors of the auxiliary signals that can be used for each digitizer device number:

Digitizer device #

Matrox Solios eA/xA Single

Matrox Solios eA/xA Dual

Matrox Solios eA/xA Quad

M_DEV0

External auxiliary I/O connector 0 and 1, and analog video input connector 0.

External auxiliary I/O connector 0 and 1, and analog video input connector 0.

External auxiliary I/O connector 0 and 1, and analog video input connector 0.

M_DEV1

External auxiliary I/O connector 0 and 1, and analog video input connector 0.

External auxiliary I/O connector 0 and 1, and analog video input connector 0.

M_DEV2

External auxiliary I/O connector 0 and 1, and analog video input connector 1.

M_DEV3

External auxiliary I/O connector 0 and 1, and analog video input connector 1.

Auxiliary I/O signals can have one or more functionalities (for example, trigger input, timer output, or user output, depending on the signal). Their possible functionalities are described in their description in the pinout table below. Shared input and output signals can be accessed by the digitizers with the specified M_DEV... number. Although a shared signal can be accessed by multiple digitizers, all the functionalities supported by the signal might not be accessible by all these digitizers. In the case of shared output signals, ensure that only one digitizer is driving the output.

This board has 4 trigger controllers per acquisition path so that on-board events (for example, acquisition and timer output) can start upon different triggers if required. Although a trigger controller might support several trigger input signals, only one signal can drive a trigger controller at any given time. For example, if you set signal A as the trigger input source for acquisition, and signal B as the trigger input source for timer 1, signal A and B must be driving different trigger controllers; if they drive the same trigger controller, an error is generated. Note that you can set a signal (for example, signal A) as the trigger input source for both acquisition and timer 1; in this case, the associated trigger controller triggers both events at the same time.

Only those auxiliary signals that have matching MIL information are included in this section. For information on internal connectors and a comprehensive list of all available input and output signals, refer to the board's installation and hardware reference manual.

Board connectors

On Matrox Solios eA/XA, there are two DVI analog video input connectors. On the bracket of the LVDS cable adapter board, there are two external auxiliary I/O connectors (DBHD-44 and DB-9); these allow you to access the signals of the 50-pin internal auxiliary I/O connector from outside the computer enclosure.

All of Matrox Solios eA/XA's connectors have auxiliary signals with matching MIL information.

Connector Name

Connector Abbreviation

Image

Description

Analog video input connectors

DVI (0 and 1)

The two analog video input connectors are DVI connectors. They are used to receive video input signals and transmit/receive timing, synchronization, and communication signals between the video source and the frame grabber.

External auxiliary I/O connector 0

DBHD-44

External auxiliary I/O connector 0 is a high-density D-subminiature 44-pin female connector, located on the bracket of the LVDS cable adapter board. This connector is used to transmit/receive auxiliary signals.

External auxiliary I/O connector 1

DB-9

External auxiliary I/O connector 1 is a standard D-subminiature 9-pin female connector, located on the bracket of the LVDS cable adapter board. This connector is used to receive opto-isolated auxiliary input signals.

Signal names and their matching MIL constants

The table below lists the auxiliary signals with their associated MIL information. Note that the MIL constants in this table are those to use with MIL 10 and later. If you are upgrading from a previous version of MIL, you should port your code using the conversion tables (MilSoliosAnalogIOConversionTable) for Matrox Solios eA/XA in the MIL release notes.

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Click to summarizeDigitizer device # Description
MIL I/O #
Pin information
Direction
User-bit information
Trigger information
Timer information
Hardware manual signal name
Click to summarizeDigitizer device #: M_DEV0

Indicates the following.

(summarize)
Click to summarizeMIL I/O #: M_AUX_IO0

Opto-isolated auxiliary signal (input) for acquisition path 0, which supports: trigger input or user input.

(summarize)
Pin information Connector: DB-9 Pin: 7+, 2-
Direction

Input

Trigger information Trigger controller: 1 on acq path 0. M_HARDWARE_PORT0; Digitizer device #: M_DEV0;
Trigger controller: 1 on acq path 0.
Hardware manual signal name P0_OPTO_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO1

TTL auxiliary signal (input) for acquisition path 0, which supports: trigger input, field polarity input, or user input.

(summarize)
Pin information Connector: DVI (0) Pin: 14
Direction

Input

Trigger information Trigger controller: 0 on acq path 0. M_HARDWARE_PORT1; Digitizer device #: M_DEV0;
Trigger controller: 0 on acq path 0.
Hardware manual signal name P0_TTL_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO2
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 35+, 34-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT2; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN0
Click to summarizeMIL I/O #: M_AUX_IO3
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for timer clock or VSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 12+, 28-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT3; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN1
Click to summarizeMIL I/O #: M_AUX_IO4
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 8+, 24-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT4; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN2
Click to summarizeMIL I/O #: M_AUX_IO5
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 39+, 38-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT5; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN3
Click to summarizeMIL I/O #: M_AUX_IO6
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 7+, 22-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT6; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN4
Click to summarizeMIL I/O #: M_AUX_IO7
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 6+, 5-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT7; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN5
Click to summarizeMIL I/O #: M_AUX_IO8
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 32+, 31-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT8; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN6
Click to summarizeMIL I/O #: M_AUX_IO9
Shared with: M_DEV1, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 1+, 16-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT9; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN7
Click to summarizeMIL I/O #: M_AUX_IO10

LVDS or TTL auxiliary signal (output) for acquisition path 0, which supports: user output, timer output, or HSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 15+, 30-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT0;
Digitizer device #: M_DEV0;
(Hardware manual user signal rank 1 : 0 on acq path 0 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV0;
Hardware manual signal name P0_LVDS/TTL_AUX_OUT0
Click to summarizeMIL I/O #: M_AUX_IO11

LVDS or TTL auxiliary signal (output) for acquisition path 0, which supports: user output, timer output, or VSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 44+, 29-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT1;
Digitizer device #: M_DEV0;
(Hardware manual user signal rank 1 : 1 on acq path 0 )
Timer information Timer: M_TIMER2; Digitizer device #: M_DEV0;
Hardware manual signal name P0_LVDS/TTL_AUX_OUT1
Click to summarizeMIL I/O #: M_AUX_IO12

TTL auxiliary signal (output) for acquisition path 0, which supports: timer output or user output.

(summarize)
Pin information Connector: DVI (0) Pin: 23
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT2;
Digitizer device #: M_DEV0;
(Hardware manual user signal rank 1 : 2 on acq path 0 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV0;
Hardware manual signal name P0_TTL_AUX(EXP)_OUT
Click to summarizeDigitizer device #: M_DEV1

Indicates the following.

(summarize)
Click to summarizeMIL I/O #: M_AUX_IO0

Opto-isolated auxiliary signal (input) for acquisition path 1, which supports: trigger input or user input.

(summarize)
Pin information Connector: DB-9 Pin: 4+, 5-
Direction

Input

Trigger information Trigger controller: 1 on acq path 1. M_HARDWARE_PORT0; Digitizer device #: M_DEV1;
Trigger controller: 1 on acq path 1.
Hardware manual signal name P1_OPTO_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO1

TTL auxiliary signal (input) for acquisition path 1, which supports: trigger input, field polarity input, or user input.

(summarize)
Pin information Connector: DVI (0) Pin: 22
Direction

Input

Trigger information Trigger controller: 0 on acq path 1. M_HARDWARE_PORT1; Digitizer device #: M_DEV1;
Trigger controller: 0 on acq path 1.
Hardware manual signal name P1_TTL_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO2
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 35+, 34-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT2; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN0
Click to summarizeMIL I/O #: M_AUX_IO3
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for timer clock or VSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 12+, 28-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT3; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN1
Click to summarizeMIL I/O #: M_AUX_IO4
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 8+, 24-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT4; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN2
Click to summarizeMIL I/O #: M_AUX_IO5
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 39+, 38-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT5; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN3
Click to summarizeMIL I/O #: M_AUX_IO6
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 7+, 22-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT6; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN4
Click to summarizeMIL I/O #: M_AUX_IO7
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 6+, 5-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT7; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN5
Click to summarizeMIL I/O #: M_AUX_IO8
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 32+, 31-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT8; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN6
Click to summarizeMIL I/O #: M_AUX_IO9
Shared with: M_DEV0, M_DEV2, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 1+, 16-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT9; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN7
Click to summarizeMIL I/O #: M_AUX_IO10

LVDS or TTL auxiliary signal (output) for acquisition path 1, which supports: user output, timer output, or HSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 43+, 42-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT0;
Digitizer device #: M_DEV1;
(Hardware manual user signal rank 1 : 0 on acq path 1 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV1;
Hardware manual signal name P1_LVDS/TTL_AUX_OUT0
Click to summarizeMIL I/O #: M_AUX_IO11

LVDS or TTL auxiliary signal (output) for acquisition path 1, which supports: user output, timer output, or VSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 11+, 27-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT1;
Digitizer device #: M_DEV1;
(Hardware manual user signal rank 1 : 1 on acq path 1 )
Timer information Timer: M_TIMER2; Digitizer device #: M_DEV1;
Hardware manual signal name P1_LVDS/TTL_AUX_OUT1
Click to summarizeMIL I/O #: M_AUX_IO12

TTL auxiliary signal (output) for acquisition path 1, which supports: timer output or user output.

(summarize)
Pin information Connector: DVI (0) Pin: 6
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT2;
Digitizer device #: M_DEV1;
(Hardware manual user signal rank 1 : 2 on acq path 1 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV1;
Hardware manual signal name P1_TTL_AUX(EXP)_OUT
Click to summarizeDigitizer device #: M_DEV2

Indicates the following.

(summarize)
Click to summarizeMIL I/O #: M_AUX_IO0

Opto-isolated auxiliary signal (input) for acquisition path 2, which supports: trigger input or user input.

(summarize)
Pin information Connector: DB-9 Pin: 1+, 6-
Direction

Input

Trigger information Trigger controller: 1 on acq path 2. M_HARDWARE_PORT0; Digitizer device #: M_DEV2;
Trigger controller: 1 on acq path 2.
Hardware manual signal name P2_OPTO_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO1

TTL auxiliary signal (input) for acquisition path 2, which supports: trigger input, field polarity input, or user input.

(summarize)
Pin information Connector: DVI (1) Pin: 14
Direction

Input

Trigger information Trigger controller: 0 on acq path 2. M_HARDWARE_PORT1; Digitizer device #: M_DEV2;
Trigger controller: 0 on acq path 2.
Hardware manual signal name P2_TTL_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO2
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 35+, 34-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT2; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN0
Click to summarizeMIL I/O #: M_AUX_IO3
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for timer clock or VSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 12+, 28-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT3; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN1
Click to summarizeMIL I/O #: M_AUX_IO4
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 8+, 24-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT4; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN2
Click to summarizeMIL I/O #: M_AUX_IO5
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 39+, 38-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT5; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN3
Click to summarizeMIL I/O #: M_AUX_IO6
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 7+, 22-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT6; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN4
Click to summarizeMIL I/O #: M_AUX_IO7
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

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Pin information Connector: DBHD-44 Pin: 6+, 5-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT7; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN5
Click to summarizeMIL I/O #: M_AUX_IO8
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 32+, 31-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT8; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN6
Click to summarizeMIL I/O #: M_AUX_IO9
Shared with: M_DEV0, M_DEV1, M_DEV3

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 1+, 16-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT9; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN7
Click to summarizeMIL I/O #: M_AUX_IO10

LVDS or TTL auxiliary signal (output) for acquisition path 2, which supports: user output, timer output, or HSYNC output.

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Pin information Connector: DBHD-44 Pin: 40+, 25-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT0;
Digitizer device #: M_DEV2;
(Hardware manual user signal rank 1 : 0 on acq path 2 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV2;
Hardware manual signal name P2_LVDS/TTL_AUX_OUT0
Click to summarizeMIL I/O #: M_AUX_IO11

LVDS or TTL auxiliary signal (output) for acquisition path 2, which supports: user output, timer output, or VSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 20+, 4-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT1;
Digitizer device #: M_DEV2;
(Hardware manual user signal rank 1 : 1 on acq path 2 )
Timer information Timer: M_TIMER2; Digitizer device #: M_DEV2;
Hardware manual signal name P2_LVDS/TTL_AUX_OUT1
Click to summarizeMIL I/O #: M_AUX_IO12

TTL auxiliary signal (output) for acquisition path 2, which supports: timer output or user output.

(summarize)
Pin information Connector: DVI (1) Pin: 23
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT2;
Digitizer device #: M_DEV2;
(Hardware manual user signal rank 1 : 2 on acq path 2 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV2;
Hardware manual signal name P2_TTL_AUX(EXP)_OUT
Click to summarizeDigitizer device #: M_DEV3

Indicates the following.

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Click to summarizeMIL I/O #: M_AUX_IO0

Opto-isolated auxiliary signal (input) for acquisition path 3, which supports: trigger input or user input.

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Pin information Connector: DB-9 Pin: 8+, 3-
Direction

Input

Trigger information Trigger controller: 1 on acq path 3. M_HARDWARE_PORT0; Digitizer device #: M_DEV3;
Trigger controller: 1 on acq path 3.
Hardware manual signal name P3_OPTO_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO1

TTL auxiliary signal (input) for acquisition path 3, which supports: trigger input, field polarity input, or user input.

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Pin information Connector: DVI (1) Pin: 22
Direction

Input

Trigger information Trigger controller: 0 on acq path 3. M_HARDWARE_PORT1; Digitizer device #: M_DEV3;
Trigger controller: 0 on acq path 3.
Hardware manual signal name P3_TTL_AUX(TRIG)_IN
Click to summarizeMIL I/O #: M_AUX_IO2
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 35+, 34-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT2; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN0
Click to summarizeMIL I/O #: M_AUX_IO3
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 0 for timer clock or VSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 12+, 28-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT3; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN1
Click to summarizeMIL I/O #: M_AUX_IO4
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 8+, 24-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT4; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN2
Click to summarizeMIL I/O #: M_AUX_IO5
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 1 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 39+, 38-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT5; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN3
Click to summarizeMIL I/O #: M_AUX_IO6
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 7+, 22-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT6; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN4
Click to summarizeMIL I/O #: M_AUX_IO7
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 2 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 6+, 5-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT7; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN5
Click to summarizeMIL I/O #: M_AUX_IO8
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 32+, 31-
Direction

Input

Trigger information Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3. M_HARDWARE_PORT8; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 2 on acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN6
Click to summarizeMIL I/O #: M_AUX_IO9
Shared with: M_DEV0, M_DEV1, M_DEV2

LVDS or TTL auxiliary signal (input), shared between all acquisition paths for trigger or user input, and dedicated to acquisition path 3 for field polarity, data valid, CSYNC, or HSYNC input.

(summarize)
Pin information Connector: DBHD-44 Pin: 1+, 16-
Direction

Input

Trigger information Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3. M_HARDWARE_PORT9; Digitizer device #: M_DEV0, M_DEV1, M_DEV2, M_DEV3;
Trigger controller: 3 on acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq path 3.
Hardware manual signal name LVDS/TTL_AUX_IN7
Click to summarizeMIL I/O #: M_AUX_IO10

LVDS or TTL auxiliary signal (output) for acquisition path 3, which supports: user output, timer output, or HSYNC output.

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Pin information Connector: DBHD-44 Pin: 33+, 18-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT0;
Digitizer device #: M_DEV3;
(Hardware manual user signal rank 1 : 0 on acq path 3 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV3;
Hardware manual signal name P3_LVDS/TTL_AUX_OUT0
Click to summarizeMIL I/O #: M_AUX_IO11

LVDS or TTL auxiliary signal (output) for acquisition path 3, which supports: user output, timer output, or VSYNC output.

(summarize)
Pin information Connector: DBHD-44 Pin: 2+, 17-
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT1;
Digitizer device #: M_DEV3;
(Hardware manual user signal rank 1 : 1 on acq path 3 )
Timer information Timer: M_TIMER2; Digitizer device #: M_DEV3;
Hardware manual signal name P3_LVDS/TTL_AUX_OUT1
Click to summarizeMIL I/O #: M_AUX_IO12

TTL auxiliary signal (output) for acquisition path 3, which supports: timer output or user output.

(summarize)
Pin information Connector: DVI (1) Pin: 6
Direction

Output

User-bit information
MIL user-bit #: M_USER_BIT2;
Digitizer device #: M_DEV3;
(Hardware manual user signal rank 1 : 2 on acq path 3 )
Timer information Timer: M_TIMER1; Digitizer device #: M_DEV3;
Hardware manual signal name P3_TTL_AUX(EXP)_OUT